The accuracy of an output voltage produced by an integrating circuit is affected by the input offset voltage of a differential amplifier circuit used in the integrating circuit. In order to realize a highly accurate integrating circuit, it is necessary to minimize the input offset voltage, which arises due to a variance in the threshold voltage (Vt) and transconductance, etc., of the input transistors of the differential amplifier circuit. A problem with the integrating circuit is that an error ascribable to the input offset voltage of a differential stage in the differential amplifier circuit accumulates in the capacitance of the feedback path, resulting in a larger error in the output voltage. That is, irrespective of the fact that the input potential of the integrating circuit is made zero, the output potential deviates from zero owing to the input offset voltage and the capacitance of the integrating circuit is charged or discharged by the shifted error voltage.
Since the input offset voltage is proportional to the reciprocal of the gain of the differential amplifier circuit, the input offset voltage can be reduced by raising the gain. One known technique for raising gain is to adopt a folded-cascode-type differential amplifier circuit in which a gate-grounded transistor is connected to the drain of a source-grounded input transistor, with opposite conductivity types being used for the source-grounded transistor and gate-grounded transistor (e.g., see the specifications of Japanese Patent Kokai Publication Nos. 2001-251146 and 9-69736).
Also known as means for diminishing the occurrence of output-voltage error due to input offset voltage is a chopping technique in which inverted and non-inverted signals in input and output stages of a differential amplifier circuit are changed over alternatingly in time-shared fashion (e.g., see the specification of Japanese Patent Kohyo Publication No. 2002-530916).
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-251146A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-9-69736
[Patent Document 3]
Japanese Patent Kohyo Publication No. JP-P2002-530916A